The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a decoder circuit of reduced size for use in addressing memory bits in integrated memory circuits.
Semiconductor memory devices are integrated circuits in which information may be stored and from which information may be extracted when desired. Each memory device is built from a plurality of memory cells in which each memory cell memorizes one binary bit of data. Although a bit of data seems insignificant, modern memory devices contain billions of memory cells to store billions of bits of information.
Modern memory device are of a variety of types such as a dynamic random access memory (DRAM), static random access memory (SRAM), video random access memory (VRAM), erasable programmable read only memory (EPROM), electrically erasable and programmable read only memories (EEPROMS), dynamic electrically alterable programmable read only memory (DEAPROM), flash memory, or other semiconductor memory devices. As these devices become more sophisticated, they require more and more memory in order to keep pace with the increasing complexity of software based applications that run on the systems. Thus, as the technology relating to memory devices has evolved, designers have tried to increase the density of the components of the memory device. For example, the electronics industry strives to decrease the size of memory cells that store the data in the memory device. This allows a larger number of memory cells to be fabricated without substantially increasing the size of the semiconductor wafer used to fabricate the memory device.
Memory devices store data in vast arrays of memory cells. Essentially, the cells are located at intersections of wordlines and bitlines (rows and columns of an array). Each cell conventionally stores a single bit of data as a logical xe2x80x9c1xe2x80x9d or a logical xe2x80x9c0xe2x80x9d and can be individually accessed or addressed. Conventionally, each cell is addressed using two multi-bit numbers. The first multi-bit number, or row address, identifies the row of the memory array in which the memory cell is located. The second multi-bit number, or column address, identifies the column of the memory array in which the desired memory cell is located. Each row address/column address combination corresponds to a single memory cell.
To access an individual memory cell, the row and column addresses are applied to inputs of row and column decoders, respectively. Conventionally, row and column decoders are fabricated using programmable logic arrays. These arrays are configured so as to select desired word and bit lines based on address signals applied to the inputs of the array. As with the array of memory cells, the decoder arrays use a portion of the surface area of the semiconductor wafer. Thus, designers also strive to reduce the surface area required for the decoder arrays.
Memory devices are fabricated using photolithographic techniques that allow semiconductor and other materials to be manipulated to form integrated circuits as is known in the art. These photolithographic techniques essentially use light that is focussed through lenses and masks to define patterns in the materials with microscopic dimensions. The equipment and techniques that are used to implement this photolithography provide a limit for the size of the circuits that can be formed with the materials. Essentially, at some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of the circuit. In other words, there is a minimum dimension that can be achieved through conventional photolithography. This minimum dimension is referred to as the xe2x80x9ccritical dimensionxe2x80x9d (CD) or minimum xe2x80x9cfeature sizexe2x80x9d (F) of the photolithographic process. The minimum feature size imposes one constraint on the size of the components of a memory device, including the decoder array. In order to keep up with the demands for higher capacity memory devices, designers search for other ways to reduce the size of the components of the memory device, including the decoder array.
As a result, the semiconductor memory devices are becoming more and more complex as the industry continues to increase the capacity of memory devices while at the same time reducing the size of the components which make up the semiconductor memory devices. The increase in capacity of memory devices is partly due to the shrinking of the components fabricated on the semiconductor die into smaller and smaller dimensions. For example, the smallest defined feature size (F) of some semiconductor memories is in the submicron range. In addition to shrinking the feature size of the circuits of semiconductor memories, optimizing the design for circuits also contributes to increased capacity for semiconductor memory devices. For example, efficient ways to implement electronic circuitry in semiconductor devices which minimize their required area on the semiconductor surface can result in space savings which can be used to increase the number of memory bits (mbits) that can be packaged in a memory device.
Because semiconductor memory devices such as dynamic random access memory (DRAM) devices are highly ordered in regular arrays, photolithographic duplication of memory cells and the circuits which access, read and write the memory cells is one way in which these circuits are manufactured. For example, a simple 3-to-8 line decoder circuit used for address decoding may be duplicated thousands of times within a semiconductor memory device. Thus, an area savings of one transistor can result in a total area savings on a semiconductor memory device of 1,000 times the area of the one transistor saved. Thus, incremental advances in the packing density of components of semiconductor memory devices can result in large advances in the total packing density and increased capacity of memory devices.
As the memory devices shrink in physical dimensions, and the electrical components on the integrated circuit are manufactured closer together, the issue of electrical noise becomes an increasing problem. For example, a wire internal to an integrated circuit may switch from a low voltage to a high voltage which may cause an adjacent wire to momentarily rise in voltage due to capacitive coupling between the wires. This increase in noise due to proximity and capacitive coupling must also be addressed as the packing density increases and the dimensions decrease.
There is a need in the art for increasing the capacity and density of memory devices and at the same time decreasing the area of components used to make up semiconductor memory devices to allow increased memory bit capacities for memories. There is also a need to address on-chip noise problems which arise due to the increased packing density.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Devices and methods are described which accord these benefits.
The present invention describes several embodiments which are designed to hold unselected decoder output lines, such as wordlines, to a voltage or ground when adjacent wordlines are selected to limit errors due to sympathetic capacitive coupling between wordlines. In one illustrative embodiment, a space saving technique for maintaining wordlines in unselected states is comprised of a common gate structure utilized across a plurality of bleed transistors which weakly pull or hold the associated wordlines to an unselected voltage level. In other embodiments, the bleed device holds the unselected wordline to an voltage or ground level while consuming a very small current. While the bleed device holds the wordlines to the unselected voltage level with a weak current, the bleed device hold may be overcome by other devices driving the wordlines with strong drive currents. Other embodiments include the use of modulated or changing control voltages on the bleed signal of the bleed devices based upon the physical arrangement and proximity of adjacent wordlines such as odd/even layouts of wordline architectures.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.